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| www.fairchildsemi.com FAN1851A Ground Fault Interrupter Features * Improved performance over industry equivalents - Tight fault current range (Typ 100A) - Temperature compensated fault current characteristics - No external trimming required * Direct interface to SCR * Supply voltage derived from AC line--26V shunt * Adjustable sensitivity * Grounded neutral fault detection * Meets UL943 standards * 450A quiescent current * Ideal for 120V or 220V systems * Package options: 8L DIP and 8L SOIC Description The FAN1851A is a controller for AC outlet ground fault interrupters. These devices detect hazardous grounding conditions (example: a pool of water or an electrical equipment connected to opposite phases of the AC line) in consumer and industrial environments. The output of the IC triggers an external SCR, which in turn opens a relay circuit breaker to prevent a harmful or lethal shock. Full advantage of the U.S. UL943 timing specification is taken to ensure maximum immunity to false triggering due to line noise. A special feature in the circuitry rapidly resets the integrating timing capacitor in the event that noise pulses introduce unwanted charging currents. Also, a flip-flop is included that ensures firing of even a slow circuit breaker relay on either of the two half-cycles of the line voltage when external full wave rectification is used. The application circuit can be configured to detect both normal faults (hot wire to ground) and grounded neutral faults. Block Diagram +VS Timing Capacitor Sensitivity Set Resistor Sense Amplifier Output ITH D3 I2 Q2 SCR Trigger Q3 Latch Q1 IF I I1 = TH for IF > 0 3ITH for IF = 0 D1 A1 Q4 IF +VS Q5 D2 10V Ground Inverting Input Non-Inverting Input REV. 2.0.1 6/17/05 FAN1851A PRODUCT SPECIFICATION Pin Assignments SCR Trigger - Input + Input Ground 1 2 3 4 8 7 6 5 +VS CT RSET Amp Out Functional Description The voltage at the supply pin is clamped to +26V by the internal shunt regulator D3. This shunt regulator also generates an artificial ground voltage for the noninverting input of A1 (shown as a +10V source). A1, Q1, and Q2 together act as a current mirror for fault current signals (which are derived from an external transformer). When a fault signal is present, the mirrored current charges the external timing capacitor until its voltage exceeds the latch trigger threshold (typically 17.5V). When this threshold is exceeded, the latch engages and Q3 turns off, allowing I2 to drive the SCR connected to the "SCR Trigger" pin. Extra Circuitry in the feedback path of A1 works with the switched current source I1 to remove any charge on CT induced by noise in the transformer. If no fault current is present, then I1 discharges CT with a current equal to 3 ITH, where ITH is the value of current set by the external RSET resistor. If fault signals are present at the input of A1 (which is held at virtual ground, +10V), one of the two current mirrors in the feedback path of A1 (Q4 and Q5) will become active, depending on which half-cycle the fault occurs. This action will raise the voltage at VS, switching I1 to a value equal to ITH, and reducing the discharge rate of CT to better allow fault currents to charge it. Notice that ITH discharges CT during both half-cycles of the line, while IF only charges CT during the half-cycle in which IF exits the "- Input" pin (since Q1 will only carry fault current in one direction). Thus, during one half-cycle, IF-ITH charges CT, while during the other half-cycle ITH discharges it. Definition of Terms Normal Fault: An unintentional electrical path, RB, between the load terminal of the hot line and the ground, as shown by the dashed lines in Figure1. Hot Hot RLOAD Line Neutral Neutral RG RG Neutral RIN Grounded Neutral Fault: An unintentional electrical path between the load terminal of the neutral line and the ground, as shown by the dashed lines in Figure 2. Hot Hot RLOAD Line Neutral GFI RB GFI Figure 1. Normal Fault Figure 2. Grounded Neutral Fault 2 REV. 2.0.1 6/17/05 PRODUCT SPECIFICATION FAN1851A Normal Fault Plus Grounded Neutral Fault: The combination of the normal fault and the grounded neutral fault, as shown by the dashed lines in Figure 3. Hot Hot RLOAD Line Neutral GFI RB Neutral RN RG Figure 3. Normal Fault Plus Grounded Neutral Fault Absolute Maximum Ratings Parameter Supply Current Power Dissipation Operating Temperature Lead Soldering Temperature, 60 seconds -40 Conditions Min Max 19 570 70 300 Units mA mW C C Thermal Characteristics Parameter Maximum Junction Temperature Maximum PD Thermal Resistance, JA TA < 50C DIP SOIC Conditions Min Max 125 468 85 150 Units C mW C/W REV. 2.0.1 6/17/05 3 FAN1851A PRODUCT SPECIFICATION DC Electrical Characteristics (TA = +25C, ISHUNT = 5 mA) Parameters Power Supply Shunt Regulator Voltage Latch Trigger Voltage Sensitivity Set Voltage Output Drive Current Output Saturation Voltage Output Saturation Resistance Output External Current Sinking Capability1 Noise Integration Sink Current Ratio Test Conditions Pin 8, Average Value Pin 7 Pin 8 to Pin 6 Pin 1 With Fault Pin 1 Without Fault Pin 1 Without Fault Pin 1 Without Fault, VPIN1 Held to 0.3V Pin 7, Ratio of Discharge Currents Between No Fault and Fault Conditions 2 2.0 Min 22 15 6 0.5 Typ 26 17.5 7 1 100 100 5 2.8 3.6 Max 30 20 8.2 2.4 240 Units V V V mA mV mA A/A Note: 1. This external applied current is in addition to the internal "output drive current" source. AC Electrical Characteristics (TA = +25C, ISHUNT = 5 mA) Parameters Normal Fault Current Normal Fault Trip Sensitivity2 Time1 1 Conditions See Figure 9 500 Fault, see Figure 10 500 Normal Fault, 2 Neutral, see Figure 10 (Note 1) Min 4.75 Typ 5 18 18 Max 5.25 Units mA mS mS Normal Fault With Grounded Neutral Fault Trip Time Notes: 1. Average of ten trials. 2. Required UL System sensitivity tolerance is 4mA to 6mA. 4 REV. 2.0.1 6/17/05 PRODUCT SPECIFICATION FAN1851A Typical Performance Characteristics (TA = +25C) Circuit of Figure 10 Fault Current on Line [mA(rms)] 1000 100 RSET = 7V IF (rms)* x (0.91) Fault Current (mA) 100 Normal Fault 10 UL943 Sense Transformer 1000:1 10 0 0.01 0.1 1 10 1 100K 1M 10M Trip Time (Seconds) Figure 4. Average Trip Time vs. Fault Current RSET () Figure 5. Normal Fault Current Threshold vs. RSET 1400 Output Drive Current @ Pin 1 (A) 1200 10 1000 800 600 400 200 0 0 5 10 15 20 25 30 35 5 mA 8 31V Pin 1 Saturation Voltage (V) 1 5 mA 8 1 V 4 31V 1 mA 1 IL A 0.1 VPIN1 4 1 mA 0.01 0.1 1 10 100 Output Voltage @ VPIN1(V) Figure 6. Output Drive Current vs. Output Voltage External Load Current (mA) Figure 7. Pin 1 Saturation Voltage vs. External Load Current, IL REV. 2.0.1 6/17/05 5 FAN1851A PRODUCT SPECIFICATION Application Information A typical ground fault interrupter circuit is shown in Figure 10. It is designed to operate on 120 VAC line voltage with 5mA normal fault sensitivity. A full-wave rectifier bridge and a 15k/2W resistor are used to supply the DC power required by the IC. A 1 F capacitor at the "+VS" pin is used to filter the ripple of the supply voltage and is also connected across the SCR to allow firing of the SCR on either half-cycle. When a fault causes the SCR to trigger, the circuit breaker is energized and line voltage is removed from the load. At this time no fault current flows and the CT discharge current increases from ITH to 3ITH (see Block Diagram). This quickly resets both the timing capacitor and the output latch. The circuit breaker can be reset and the line voltage again supplied to the load, assuming the fault has been removed. A 1000:1 sense transformer is used to detect the normal fault. The fault current, which is basically the difference in current between the hot and neutral lines, is stepped down by 1000 and fed into the input pin of the operational amplifier through a 10F capacitor. The 0.0033F capacitor between the "- Input" pin and the "+ Input" pin and the 200pF capacitor between "+ Input" and "Ground" pins are added to obtain better noise immunity. The normal fault sensitivity is determined by the timing capacitor discharging current, ITH. ITH can be calculated by: I TH 7V = ------------ / 2 R SET (1) The correct value for RSET can also be determined from the characteristic curve that plots equation (3). Note that this is an approximate calculation; the exact value of RSET depends on the specific sense transformer used and FAN1851A tolerances. Inasmuch as UL943 specifies a sensitivity "window" of 4mA to 6mA, a provision should be made to adjust RSET with a potentiometer. Independent of setting sensitivity, the desired integration time can be obtained through proper selection of the timing capacitor, CT. Due to the large number of variables involved, proper selection of CT is best done empirically. The following design example should only be used as a guideline. Assume the goal is to meet UL943 timing requirements. Also assume that worst case timing occurs during GFI start-up (S1 closure) with both a heavy normal fault and a 2 grounded neutral fault present. This situation is shown in Figure 8. S1 Hot Line Neutral GFI Neutral RN 0.4 RB 500 I RB 500 (0.2)I Hot (0.8)I At the decision point, the average fault current just equals the threshold current, ITH. I TH I F ( rms ) = ------------------ x 0.91 2 (2) Figure 8. Example UL943 specifies 25ms average trip time under these conditions. Calculation of CT based upon charging currents due to normal fault only is as follows: 1. Start with a 25ms specification. Subtract 3ms GFI turn-on time (15k and 1F). Subtract 8ms potential loss of one half-cycle due to fault current sense of half-cycles only. Subtract 4ms time required to open a sluggish circuit breaker. This gives a total 10ms maximum integration time that could be allowed. To generate 8ms value of integration time that accommodates component tolerances and other variables: IxT C T = ----------V (5) Where IF(rms) is the rms input fault current to the operational amplifier and the factor of 2 is due to the fact that IF charges the timing capacitor only during one half-cycle, while ITH discharges the capacitor continuously. The factor 0.91 converts the rms value to an average value. Combining equations (1) and (2) we have: 7V R SET = ----------------------------------I F ( rms ) x 0.91 (3) 2. 3. For example, to obtain 5mA(rms) sensitivity for the circuit in Figure 7 we have: 7V R SET = ----------------------------- = 1.5M 5 mA x 0.91 ----------------------------1000 (4) 4. 6 REV. 2.0.1 6/17/05 PRODUCT SPECIFICATION FAN1851A where: T = integration time V = threshold voltage I = average fault current into CT 120 V AC ( rms ) I = ------------------------------------ RB heavy fault current generated (swamps ITH) RN ---------------------- RG + RN portion of fault current shunted around GFI In practice, the actual value of CT will have to be modified to include the effects of the neutral loop upon the net charging current. The effect of neutral loop induced currents is difficult to quantify, but typically they sum with normal fault currents, thus allowing a larger value of CT. For UL943 requirements, 0.015F has been found to be the best compromise between timing and noise. For those GFI standards not requiring grounded neutral detection, a still larger value capacity can be used and better noise immunity obtained. The larger capacitor can be accommodated because RN and RG are not present, allowing the full fault current, I, to enter the GFI. (6) In Figure 10, grounded neutral detection is accomplished by feeding the neutral coil with 120Hz energy continuously and allowing some of the energy to couple into the sense transformer during conditions of neutral fault. Transformers may be obtained from Magnetic Metals, Inc., (http://www.magmet.com). 1 turn x ------------------------ 1000 turns current division of input sense transformer x 1 - 2 CT charging on halfcycles only x ( 0.91 ) rms to average conversion therefore: 0.4 1 120 x -------------------- x ----------- x 1 x ( 0.91 ) -------- 500 1.6 + 0.4 1000 2 C T = ----------------------------------------------------------------------------------------------------------------- x 0.008 17.5 C T = 0.01 F (7) REV. 2.0.1 6/17/05 7 FAN1851A PRODUCT SPECIFICATION Application Circuits FAN1851A 7 1 CT 0.002 ISHUNT A 1K 300 mV 31V 1.5M Timing Cap SCR Trigger Op Amp Output +VS -In +In RSET GND 2 3 6 4 100K 0.047 F 5 8 800 Hz Figure 9. Normal Fault Sensitivity Test Circuit Gnd/Neutral Coil Hot Load Neutral Circuit Breaker 0.01/400V High Coil MOV 200:1 Sense Coil 1000:1 Line FAN1851A 7 Timing Cap -In 2 1.0 F Tant 15K/2W 1 CT 0.015 SCR 5 8 0.01 RSET* SCR Trigger Op Amp Output +VS +In RSET GND 0.0033 3 6 4 200 pF 0.01/400V 10 F Tant *Adjust RSET for desired sensitivity. Figure 10. 120 Hz Neutral Transformer Application 8 REV. 2.0.1 6/17/05 FAN1851A PRODUCT SPECIFICATION Mechanical Dimensions 8-Lead Plastic DIP Package 6.40 0.20 0.252 0.008 0.79 ) 0.031 #1 #8 9.60 MAX 0.378 9.20 0.20 0.362 0.008 #4 #5 2.54 0.100 5.08 MAX 0.200 7.62 0.300 3.40 0.20 0.134 0.008 3.30 0.30 0.130 0.012 0.33 0.013 MIN 0.25 -0.05 0~15 +0.10 0.010 -0.002 +0.004 Dimensions in Millimeters 9 0.018 0.004 1.524 0.10 0.060 0.004 REV. 2.0.1 6/17/05 0.46 0.10 ( FAN1851A PRODUCT SPECIFICATION Mechanical Dimensions (continued) 8-Lead Plastic SOIC Package Symbol A A1 B C D E e H h L N ccc Inches Min. .053 .004 .013 .008 .189 Max. .069 .010 .020 .010 .197 Millimeters Min. 1.35 0.10 0.33 0.20 4.80 Max. 1.75 0.25 0.51 0.25 5.00 5 2 2 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals. .150 .158 .050 BSC .228 .010 .016 8 0 -- 8 .004 .244 .020 .050 3.81 4.01 1.27 BSC 5.79 0.25 0.40 8 0 -- 8 0.10 6.20 0.50 1.27 3 6 8 5 E H 1 4 D A1 A SEATING PLANE B -C- LEAD COPLANARITY ccc C h x 45 C e L 10 REV. 2.0.1 6/17/05 FAN1851A PRODUCT SPECIFICATION Ordering Information Part Number FAN1851AN FAN1851AMX Package 8-lead Plastic DIP 8-lead Plastic SOIC Pb-Free Yes Yes Operating Temperature Range Packing Method -40C to +70C -40C to +70C Rail Tape and Reel DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com REV. 2.0.1 6/17/05 (c) 2005 Fairchild Semiconductor Corporation 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. |
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